nsc800 National Semiconductor Corporation, nsc800 Datasheet - Page 35

• Manufacturer Part Number: nsc800
• Description: Nsc800tm High-performance Low-power Cmos Microprocessor
• Manufacturer: National Semiconductor Corporation

12 5 16-Bit Loads
PUSH
Push the contents of register pair qq onto the memory
stack
(SP – 1)
(SP – 2)
SP
Timing
Addressing Mode
Timing
Addressing Mode
MEMORY TO REGISTER
LD
Load 16-bit register from memory location nn
rr
rr
Timing
Addressing Mode
7 6
7
1
1 1 N
1 1
7
0
L
H
6
1
6
0
n (high-order byte)
n (low-order byte)
rr (nn)
(nn)
SP
(nn
5
5
1
5
1
X
rs
qq
b
4
a
4
0
qq
qq
4 3 2 1 0
1 1 1 0 1
0 0 1 0 1
2
1)
H
L
3
0
3
1
2
1
2
0
1
0
1
1
0
1
0
0
No flags affected
M cycles 3
T states 11 (5 3 3)
Source Register
Destination Register Indirect
(Stack)
M cycles 3
T states 15 (4 5 3 3)
Source Register
Destination Register Indirect
(Stack)
No flags affected
M cycles 5
T states 16 (4 3 3 3 3)
Source Direct
Destination Register
(Continued)
PUSH BC
PUSH DE
PUSH HL
PUSH AF
LD HL (nn)
(note an alternate
opcode below)
PUSH IX (for N
PUSH IY (for N
X
X
e
e
0)
1)
35
Timing
Addressing Mode
Timing
Addressing Mode
POP
Pop the contents of the memory stack to register qq
qq
qq
SP
Timing
Addressing Mode
Timing
Addressing Mode
7 6
1 1 N
0 0
7 6
1 1 N
1 1
7
1
0
7
1
L
H
6
1
1
6
1
n (high-order byte)
n (high-order byte)
n (low-order byte)
n (low-order byte)
SP
5
1
5
5
1
5
1
qq
(SP)
(SP
X
X
rp
rs
a
4
0
4
4 3 2 1 0
1 1 1 0 1
0 1 0 1 0
4 3 2 1 0
1 1 1 0 1
0 0 0 0 1
a
2
3
1
0
3
0
1)
2
1
0
2
0
1
0
1
1
0
0
1
1
0
1
M cycles 6
T states 20 (4 4 3 3 3 3)
Source Direct
Destination Register
M cycles 6
T states 20 (4 4 3 3 3 3)
Source Direct
Destination Register
No flags affected
M cycles 3
T states 10 (4 3 3)
Source Register Indirect
(Stack)
Destination Register
M cycles 4
T states 14 (4 4 3 3)
Source Register Indirect
(Stack)
Destination Register
POP BC
POP DE
POP HL
POP AF
LD BC (nn)
LD DE (nn)
LD HL (nn)
LD SP (nn)
LD IX (nn)(for N
LD IY (nn) (for N
POP IX (for N
POP IY (for N
X
X
e
e
X
X
0)
1)
e
e
0)
1)