mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 410
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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SIZ[1:0], TM[2:0]
General Operation of External Master Transfers
Note the following regarding external master accesses:
External master transfers that use the MCF5307 to drive memory control signals and TA
are like normal MCF5307 transfers. Figure 18-24 shows timing for basic back-to-back bus
cycles during an external master transfer.
R/W is asserted high for reads and low for writes; otherwise, the transfers are the same. In
Figure 18-24, the MCF5307 chip select’s internal transfer acknowledge is enabled and the
MCF5307 drives TA as an output after a programmed number of wait states.
18-22
A[31:0], TT[1:0]
• For the MCF5307 to assert a CSx during external master accesses, CSMRn[AM]
• To enable DRAM control signals during external master accesses, DCMRn[AM]
• During external master bus cycles, either TS or AS (but not both) should be driven
HOLDREQ
BE/BWE
1
2
BG, BD
This signal is driven by the processor for an external master transfer.
Depending on programming, these signals may or may not be driven by the processor.
BCLKO
D[31:0]
must be set. External master hits use the corresponding CSCRn settings for
auto-acknowledge, byte enables, and wait states. See Section 10.4.1.3, “Chip-Select
Control Registers (CSCR0–CSCR7).”
must be set.
to the MCF5307. Driving both during a bus cycle causes indeterminate results.
CS
BR
R/W
TA
TIP
AS
TS
1
1
1
2
2
Figure 18-24. Basic No-Wait-State External Master Access
C1
Freescale Semiconductor, Inc.
C2
For More Information On This Product,
C3
Go to: www.freescale.com
MCF5307 User’s Manual
C4
C5
External Master
C6
C7
C8
C9
C10
C11
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