mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 68
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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Programming Model
2.2.1.3 Stack Pointer (A7, SP)
The processor core supports a single hardware stack pointer (A7) used during stacking for
subroutine calls, returns, and exception handling. The stack pointer is implicitly referenced
by certain operations and can be explicitly referenced by any instruction specifying an
address register. The initial value of A7 is loaded from the reset exception vector, address
0x0000. The same register is used for user and supervisor modes, and may be used for word
and longword operations.
A subroutine call saves the program counter (PC) on the stack and the return restores the
PC from the stack. The PC and the status register (SR) are saved on the stack during
exception and interrupt processing. The return from exception instruction restores SR and
PC values from the stack.
2.2.1.4 Program Counter (PC)
The PC holds the address of the executing instruction. For sequential instructions, the
processor automatically increments PC. When program flow changes, the PC is updated
with the target instruction. For some instructions, the PC specifies the base address for
PC-relative operand addressing modes.
2.2.1.5 Condition Code Register (CCR)
The CCR, Figure 2-4, occupies SR[7–0], as shown in Figure 2-3. CCR[4–0] are indicator
flags based on results generated by arithmetic operations.
2-28
Bits
6–5
Table 2-1 describes the CCR fieldsMAC Programming ModelFigure 2-3 shows the registers in the MAC portion of the user programming model. These registers are described as follows:Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations.
7
4
3
2
Name
—
P
X
N
Z
Branch prediction bit. Alters the static prediction algorithm used by the branch acceleration logic in the
IFP on forward conditional branches.
0 Predicted as not-taken.
1 Predicted as taken.
Reserved, should be cleared.
Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not
affected or set to a specified result. Also used as an input operand for multiple-precision arithmetic.
Negative condition code bit. Set if the msb of the result is set; otherwise cleared.
Zero condition code bit. Set if the result equals zero; otherwise cleared.
Reset
Field
R/W
Freescale Semiconductor, Inc.
R/W
P
For More Information On This Product,
7
0
Table 2-1. CCR Field Descriptions
6
Go to: www.freescale.com
MCF5307 User’s Manual
00
—
R
5
R/W
X
4
Description
R/W
N
3
Undefined
R/W
Z
2
R/W
V
1
R/W
C
0
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