ics9248-134 ETC-unknow, ics9248-134 Datasheet
ics9248-134
Related parts for ics9248-134
ics9248-134 Summary of contents
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-134 1 48 VDDL ...
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... ICS9248-134 General Description The ICS9248-134 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9212-01. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB ...
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... ICS9248-134 ...
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... ICS9248-134 Byte 1: CPU, Active/Inactive Register (1 = enable disable Notes: 1. Inactive means outputs are held LOW and are disabled from switching ...
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... To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From target Freq 2.5 V +/-5% (unless otherwise stated) DDL CONDITIONS pF; Select @ 100 MHz pF; Select @ 133 MHz pF; PWRDWN ICS9248-134 +0.5 V MIN TYP MAX -0.3 0 2.0 ...
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... ICS9248-134 Group Offset 70º 3.3 V +/-5 GROUP OFFSET CPU to 3V66 0.0-1.5 ns; CPU leads. 3V66 to PCI 0.5-4.0 ns; 3V66 leads. CPU to IOAPIC 0.5-4.0 ns; CPU leads. CPU to PCI 0.5-4.0 ns; CPU leads. 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPUCLK 70º 3.3 V +/-5 PARAMETER ...
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... 1.5 V, PCICLK T (F: 1.5 V, PCICLK T (8:10 1.5 V, PCICLK T (F:10 1 ICS9248-134 MIN TYP MAX UNITS 2.4 3.1 V 0.17 0.4 V - 250 ps 173 500 ps MIN ...
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... ICS9248-134 Electrical Characteristics - 48 MHz, 24_48 MHz 70º 3.3 V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP5 1 Output Impedance R DSN5 Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current I OL5 1 Rise Time Fall Time t f5 ...
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... DDL L CONDITIONS *(0. *(0. - ICS9248-134 MIN TYP MAX UNITS 13 13 2.24 V 0.31 0.4 V - 139 250 ps 245 500 ps ...
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... ICS9248-134 Power Management Features Note: 1. LOW means outputs held static LOW as per latency requirement next page means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs. ...
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... ACK ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The ICS9248-134 2 C programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK ...
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... ICS9248-134 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. ...
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-134 In Millimeters In Inches COMMON DIMENSIONS ...