ics9248-189 ETC-unknow, ics9248-189 Datasheet

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ics9248-189

Manufacturer Part Number
ics9248-189
Description
Clock Generator Mobile System
Manufacturer
ETC-unknow
Datasheet
AMD - K7™ Clock Generator for Mobile System
Third party brands and names are the property of their respective owners.
Recommended Application:
VIA K7/KN/KX-133 style chipset
Output Features:
Features:
Key Specifications:
Block Diagram
SDRAM_STOP#
9248-189 Rev - 08/10/01
CPU_STOP#
CLK_STOP#
BUFFER_IN
PCI_STOP#
SEL24_48#
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
7 - SDRAM @ 3.3V
8 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Up to 166MHz frequency support
Support power management via hardware select CPU
stop, CLOCK stop, PCI stop, and SDRAM stop
Support power management via I
Spread spectrum for EMI control
(± 0.25% to ± 0.06% center, or 0 to -0.5% or -1.0% down
spread)
Uses external 14.318MHz crystal
CPU - CPU Skew: <175ps
CPU - SDRAM Skew: ±125ps
CPU - PCI Skew: ±100ps
PCI - PCI Skew: <500ps
FS (3:0)
SDATA
SCLK
PD#
X2
X1
Integrated
Circuit
Systems, Inc.
Spectrum
PLL2
XTAL
OSC
Spread
Config.
Control
PLL1
Logic
Reg.
DIVDER
DIVIDER
DIVDER
SDRAM
CPU
PCI
/ 2
2
C programing
Stop
Stop
Stop
3
7
6
48MHz
24_48MHz
CPUCLK_CS
PCICLK (6:0)
PCICLK_F
SDRAM (5:0)
SDRAM_F
REF (2:0)
CPUCLKT0
CPUCLKC0
Functionality
Note: For a complete functionality table please see table in
page 3.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
*SEL24_48#/24_48MHz
F
0
0
0
0
S
1
1
1
1
* Internal Pull-up Resistor of 120K to VDD
1
2
2
*SDRAM_STOP#
*FS2/PCICLK_F
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
These outputs can be set to 1X or 1.5X strength
These outputs have double strength to drive 2 loads.
*FS1/PCICLK0
through I
*PCI_STOP#
*FS0/48MHZ
F
BUFFER_IN
48-Pin 300mil SSOP & 240mil TSSOP
S
0
0
0
0
1
1
1
1
VDDREF
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
1
VDDPCI
VDDPCI
VDD48
AVDD
GND
GND
GND
GND
F
X1
X2
2
S
0
0
0
0
1
1
1
1
C
0
Pin Configuration
1
1
1
1
1
1
1
1
C
0
3
0
3
0
3
0
3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Advance Information
P
0
3
0
3
0
3
0
3
1
2
3
4
5
6
7
8
9
0 .
3 .
0 .
3 .
0 .
3 .
0 .
3 .
U
0
3
0
3
0
3
0
3
3
3
3
3
3
3
3
3
P
3
3
3
3
3
3
3
. 3
C
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 3
ICS9248-189
I
3
3
3
3
3
3
3
0
0
+
+
+
+
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S
- /
- /
o t
o t
- /
- /
p
. 0
. 0
-
-
r
0
0
a e
5 3
5 3
0
0
6 .
6 .
5 .
5 .
N
N
%
%
%
%
d
%
%
o
o
REF0
REF
REF2/FS3
GND
GND
VDD
CPUCLK_CS
CPUCLKT0
CPUCLKC0
CPU_STOP#*
CLK_STOP#*/
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
C
C
P
S
C
C
S
D
D
e
e
r e
p
p
e
e
t n
t n
o
o
e r
t n
t n
e r
1
e c
w
w
1
r e
r e
d a
r e
r e
d a
n
n
n
S
S
S
S
S
S
a t
p
p
*
p
p
p
p
e r
e r
2
2
e g
e r
e r
e r
e r
d a
d a
PD#
d a
d a
d a
d a

Related parts for ics9248-189

ics9248-189 Summary of contents

Page 1

... VDDA = VDD for Core PLL SDRAM_F VDDREF = REF, Xtal ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS9248-189 Advance Information Pin Configuration 48 1 REF0 47 ...

Page 2

... ICS9248-189 Advance Information General Description The ICS9248-189 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-189 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...

Page 3

... ICS9248-189 Advance Information ...

Page 4

... ICS9248-189 Advance Information Byte 0: CPU, Active/Inactive Register (1= enable disable ...

Page 5

... ICS9248-189 Advance Information ...

Page 6

... ICS9248-189 Advance Information Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 7

... Note 2 Note 2 Note required for switching, where /2-150mV; Max=(Vpullup (external) 7 ICS9248-189 Advance Information MIN TYP MAX UNITS 2.4 0.4 - MIN TYP MAX 1 1.2 0.4 18 0.9 0.9 V pullup(external) 0.4 + 0.6 V pullup(external) 0.2 + 0.6 550 ...

Page 8

... ICS9248-189 Advance Information Electrical Characteristics - CPUCLK_CS 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B 1 Rise Time t r2B 1 Fall Time t f2B 1 Duty Cycle d t2B 1 Skew t sk2B 1 Jitter, Cycle-to-cycle ...

Page 9

... L CONDITIONS ICS9248-189 Advance Information MIN TYP MAX UNITS 2.6 V 0 200 ps MIN TYP MAX UNITS 2.4 V 0 ...

Page 10

... ICS9248-189 Advance Information General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...

Page 11

... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-189 Advance Information ...

Page 12

... VCO Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-189 device shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. CLK_STOP input pin which stops all clocks, expcpt XTAL and CPUCLKT0/CPUCLKC0 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. ...

Page 13

... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-189. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...

Page 14

... ICS9248-189 Advance Information Ordering Information ICS9248yF-189-T Example: ICS XXXX PPP - T Third party brands and names are the property of their respective owners. SYMBOL VARIATIONS N 48 Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) ...

Page 15

... N 48 G=TSSOP ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and 15 other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS9248-189 Advance Information In Millimeters In Inches COMMON DIMENSIONS MIN MAX MIN ...

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