ics9248-141 ETC-unknow, ics9248-141 Datasheet

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ics9248-141

Manufacturer Part Number
ics9248-141
Description
System Clock With 166mhz Processor Support
Manufacturer
ETC-unknow
Datasheet
AMD - K7™ System Clock Chip
Third party brands and names are the property of their respective owners.
Recommended Application:
VIA KX133 style chipset
Output Features:
Features:
Block Diagram
CPU_STOP#
9248-141 Rev B 01/18/01
SEL24_48#
BUFFER IN
FS (3:0)
1 - Differential pair open drain CPU clocks
1 - Single-ended open drain CPU clock
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Up to 166MHz frequency support
Support power management: CPU stop and Power down
Mode from I
Spread spectrum for EMI control
(± 0.25% center spread).
Uses external 14.318MHz crystal
SDATA
SCLK
PD#
X2
X1
XTAL
OSC
Spectrum
PLL2
2
Spread
Control
Config.
Logic
PLL1
Integrated
Circuit
Systems, Inc.
C programming.
Reg.
DIVDER
DIVDER
DRIVER
SDRAM
CPU
PCI
/ 2
Stop
48MHz
24_48MHz
CPUCLKC0
CPUCLKT (1:0)
PCICLK (4:0)
PCICLK_F
SDRAM (11:0)
SDRAM_OUT
REF (1:0)
*SEL24_48#/PCICLK1
REF0/CPU_STOP#*
*MODE/PCICLK_F
Functionality
F
*FS3/PCICLK0
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3
BUFFER IN
* Internal Pull-up Resistor of 120K to VDD
SDRAM11
SDRAM10
PCICLK2
PCICLK3
PCICLK4
VDDSDR
SDRAM9
SDRAM8
VDDREF
VDDPCI
VDDPCI
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
SDATA
SCLK
GND
GND
GND
GND
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X1
X2
2
48-Pin 300mil SSOP
Pin Configuration
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
1
2
3
4
5
6
7
8
9
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
ICS9248-141
(
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
1 1
1 1
1 1
1 1
1 1
3 1
9
9
M
C
. 0
. 5
. 1
. 2
. 0
. 3
. 5
. 0
. 7
. 9
. 0
. 1
. 3
. 5
. 7
. 3
P
H
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0 0
0 0
U
0 0
0 0
0 9
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 3
) z
REF1/FS2*
GND
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24/48MHz/FS1*
P
(
C
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
M
C I
. 0
. 1
. 3
. 4
. 3
. 5
. 5
. 6
. 7
. 7
. 9
. 4
. 3
. 6
. 8
. 3
H
0 0
7 6
7 6
0 0
7 5
3 3
0 0
3 3
7 6
3 3
7 6
0 0
7 6
3 3
0 0
3 3
L
) z
K

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ics9248-141 Summary of contents

Page 1

... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is ICS9248-141 48 REF1/FS2* 47 GND 46 CPUCLKT1 45 ...

Page 2

... ICS9248-141 Pin Descriptions ...

Page 3

... General Description The ICS9248-141 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-141 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...

Page 4

... ICS9248-141 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...

Page 5

... Note: Don’t write into this register, writing into this register can cause malfunction 5 ICS9248-141 ...

Page 6

... ICS9248-141 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 7

... CPU0 OH OL CPUT1 Note 2 Note 2 Note 3 CPU0 between crossing points CPUT1 @ 50% 90,100,133 MHz required for switching, where ICS9248-141 MIN TYP MAX UNITS 2.4 0.4 -22 16 1.6 4.0 1.8 4 500 1000 MIN TYP MAX ...

Page 8

... ICS9248-141 Electrical Characteristics - PCICLK 70C 3.3V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP1B 1 Output Impedance R DSN1B Output High Voltage V OH1 Output Low Voltage V OL1 I Output High Current OH1 I Output Low Current OL1 1 Rise Time Fall Time Duty Cycle ...

Page 9

... - ICS9248-141 MIN TYP MAX UNITS 2.4 V 0 1.3 4.0 ns 1.3 4 150 500 ps MIN TYP MAX UNITS ...

Page 10

... ICS9248-141 General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...

Page 11

... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-141 ...

Page 12

... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-141 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...

Page 13

... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-141. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...

Page 14

... ICS9248-141 Ordering Information ICS9248yF-141-T Example: ICS XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) Package Type Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix Third party brands and names are the property of their respective owners ...

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