ics9248-172 ETC-unknow, ics9248-172 Datasheet
ics9248-172
Related parts for ics9248-172
ics9248-172 Summary of contents
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... Note: PCICLK = 33.33MHz AGP = 66.66MHz ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS9248-172 Advance Information 48 1 GND 2 47 CPUCLK0 ...
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... ICS9248-172 Advance Information Pin Descriptions PIN N U MBER PIN 1, APIC 11, 16, 23, 29 34, 41 17, 21 FS0 7 REF0 2, 3 FS1 PCICLK FS2 PCICLK ...
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... General Description The ICS9248-172 is a main clock synthesizer chip for PII/III based systems with ALI 1651 style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-172 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... ICS9248-172 Advance Information Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...
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... Inactive means outputs are held LOW and are disabled from switching Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 5 ICS9248-172 Advance Information ...
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... ICS9248-172 Advance Information Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...
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... ICS9248-172 Advance Information M IN TYP M AX UNITS 2 V 0 1 250 ps 250 ps 150 ps MIN TYP MAX UNITS 2.4 V 0 ...
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... ICS9248-172 Advance Information Electrical Characteristics - SDRAM 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH3 Output Low Voltage V OL3 Output High Current I OH3 Output Low Current I OL3 1 Rise Time Fall Time Duty Cycle Skew T sk1 Propagation Delay ...
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... Third party brands and names are the property of their respective owners. = 2.5 V +/-5 (unless otherwise stated) DDL L CONDITIONS ICS9248-172 Advance Information MIN TYP MAX UNITS 2.4 V 0 ...
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... ICS9248-172 Advance Information General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ...
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... The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig ICS9248-172 Advance Information ...
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... Advance Information PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-172 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-172 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-172 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-172. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... VARIATIONS N 48 F=SSOP ICS Standard Device PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. 15 Characteristic data and other specifications are subject to change without notice. ICS9248-172 Advance Information In Millimeters In Inches COMMON DIMENSIONS MIN MAX MIN MAX 2.413 2.794 ...
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... ICS9248-172 Advance Information 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICS9248yG-172-T Example: ICS XXXX PPP - T Third party brands and names are the property of their respective owners. SYMBOL aaa VARIATIONS N 48 Designation for tape and reel packaging ...