ics9248-110 ETC-unknow, ics9248-110 Datasheet
ics9248-110
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ics9248-110 Summary of contents
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-110 1 48 VDDREF ...
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... ICS9248-110 Pin Descriptions ...
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... General Description The ICS9248-110 is a main clock synthesizer chip for AMD-K7 based systems. This provides all clocks required for such a system when used with a Zero Delay Buffer Chip such as the ICS9179-06. Spread spectrum may be enabled through I 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-110 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... ICS9248-110 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-110 used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-110 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-110 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... ICS9248-110 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 110 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function ...
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... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The 7 ICS9248-110 2 C programming. How to Read: Controller (Host) ICS (Slave/Receiver) Start Bit Address D3 (H) ...
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... ICS9248-110 Command Bitmaps Byte 6: SDRAM Clock & Generator Mode Control Register Bit 7 Spread Spectrum enable (+/- 0.25% center spread) 1=ON 0=OFF Bit 3 Bit 3,2, 6 ...
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... " " ICS9248-110 " " ...
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... ICS9248-110 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...
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... Note 2 Note 2 Note required for switching, where ICS9248-110 MIN TYP MAX UNITS 2.4 V 0 2.6 4.0 ns 2.5 4 320 700 ps MIN TYP MAX UNITS ...
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... ICS9248-110 Electrical Characteristics - PCICLK 70C 3.3V +/-5 ETER SYM BOL 1 Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current ...
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... - ICS9248-110 MIN TYP MAX UNITS 0 200 ps 288 450 ps ...
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... ICS9248-110 Ordering Information ICS9248yF-110 Example: ICS XXXX PPP Pattern Number ( digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS Standard Device Third party brands and names are the property of their respective owners ...