pcf8535 NXP Semiconductors, pcf8535 Datasheet - Page 25

• Manufacturer Part Number: pcf8535
• Description: 65 X 133 Pixel Matrix Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.16
Data accesses to the PCF8535 can be broken down into
two areas, those that define the operating mode of the
device and those that fill the display RAM; the distinction
being the D/C bit. When bit D/C = 0, the device will
respond to instructions as defined in Table 16. When bit
D/C = 1, the device will store data into the RAM. Data may
be written to the device that is independent to the presence
of the display clock.
There are 4 instruction types:
1. Define PCF8535 functions such as display
2. Set internal RAM addresses
3. Perform data transfer with internal RAM
4. Others.
In normal use, type 3 instructions are the most frequently
used. To lessen the MPU program load, automatic
incrementing by one of the internal RAM address pointers
after each data write is implemented.
The instruction set is broken down into several pages,
each command page being individually addressed via the
H[2:0] bits.
7.16.1
This page is special in that it is accessible independently
of the H bits. This page is mainly used as a stepping stone
to other pages. Sending the ‘Default H[2:0]’ command will
cause an immediate step to the ‘Function and RAM
command page’ which will allow the H[2:0] bits to be set.
7.16.2
7.16.2.1
Setting H[2:0] will move the user immediately to the
required command page. Pages not listed should not be
accessed as the behaviour is not defined.
7.16.2.2
PD
When PD = 1, the LCD driver is in Power-down mode:
2001 Nov 07
All LCD outputs at V
Oscillator off
V
I
RAM contents are not cleared; RAM data can be written
Register settings remain unchanged.
65
2
LCDIN
C-bus interface accesses are possible
configuration, etc.
Instruction set
RAM
F
may be disconnected
133 pixel matrix driver
UNCTION AND
Command page
Function set
READ
/
WRITE COMMAND PAGE
SS
RAM
COMMAND PAGE
25
V
When V = 0, horizontal addressing is selected. When
V = 1, vertical addressing is selected. The behaviour is
described in Section 7.15.
7.16.2.3
The XM
may be considered to be the Most Significant Bit (MSB) of
an 8-bit X address. The behaviour is described in
Section 7.15.
7.16.2.4
The Y address is used as a pointer to the RAM for RAM
writing. The range is 0 to 8. Each bank corresponds to a
set of 8 rows; the only exception being bank 8, which
contains the icon data and is only 1-bit deep (see
Table 13).
Table 13 Y address pointer
Y[3]
0
0
0
0
0
0
0
0
1
0
bit extends the RAM into a second page. The bit
Y[2]
RAM page
Set Y address of RAM
0
0
0
0
1
1
1
1
0
Y[1]
0
0
1
1
0
0
1
1
0
Y[0]
0
1
0
1
0
1
0
1
0
bank 0
bank 1
bank 2
bank 3
bank 4
bank 5
bank 6
bank 7
bank 8
(icons)
BANK
Product specification
PCF8535
R0 to R7
R8 to R15
R16 to R23
R24 to R31
R32 to R39
R40 to R47
R48 to R55
R56 to R63
R64
ROWS