pcf8535 NXP Semiconductors, pcf8535 Datasheet - Page 32

• Manufacturer Part Number: pcf8535
• Description: 65 X 133 Pixel Matrix Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.17.2
The PCF8535 is a slave receiver/transmitter. If data is to
be read from the device the SDAOUT pad must be
connected, otherwise SDAOUT is unused.
Before any data is transmitted on the I
which should respond is addressed. Four slave
addresses, 0111100, 0111101, 0111110 and 0111111 are
reserved for the PCF8535. The Least Significant Bits
(LSBs) of the slave address is set by connecting
SA1 and SA0 to either logic 0 (V
A sequence is initiated with a START condition (S) from
the I
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I
After the acknowledgement cycle of a write, a control byte
follows which defines the destination for the forthcoming
data byte and the mode for subsequent bytes. For a read,
Table 19 Co and D/C definitions
2001 Nov 07
handbook, full pagewidth
D/C
BIT
Co
65
2
C-bus master which is followed by the slave address.
S 0 1 1 1 1
VALUE
I
2
133 pixel matrix driver
C-
0
1
0
1
slave address
BUS PROTOCOL
R/W
n.a. last control byte to be sent and only a stream of data bytes are allowed to follow; this stream
n.a. another control byte will follow the data byte unless a STOP or RE-START condition is
0
1
0
1
S
A
1
acknowledgement
from PCF8535
S
A
0
R/W
may only be terminated by a STOP or RE-START condition
received
data byte will be decoded and used to set up the device
data byte will return the contents of the currently selected status register
data byte will be stored in the display RAM
no provision for RAM read back is provided
0 A
Co
1
D/C
Fig.25 Master transmits to slave receiver; write mode.
SS
) or logic 1 (V
control byte
2
2
C-bus transfer.
C-bus, the device
acknowledgement
from PCF8535
2n
A
0 bytes
DD
).
data byte
32
acknowledgement
the PCF8535 will immediately start to output the requested
data until a NOT acknowledge is transmitted by the
master. The sequence should be terminated by a STOP in
the event that no further access is required for the time
being, or by a RE-START should further access be
required.
For ease of operation a continuation bit Co has been
included. This bit allows the user to set-up the chip
configuration and transmit RAM data in one access. A data
selection bit, D/C, defines the destination for data. These
bits are contained in the control byte. DB5 to DB0 should
be set to logic 0. These bits are reserved for future
expansion.
An example of a write access is given in Fig.25. Here,
multiple instruction data is sent, followed by multiple
display bytes.
An example of a read access is given in Fig.26.
from PCF8535
A
ACTION
Co
0
D/C
control byte
1 byte
acknowledgement
from PCF8535
A
MSB . . . . . . . . . . . LSB
data byte
n
MGS682
0 bytes
Product specification
acknowledgement
from PCF8535
PCF8535
data pointer
update
A P