pcf8535 NXP Semiconductors, pcf8535 Datasheet - Page 7

• Manufacturer Part Number: pcf8535
• Description: 65 X 133 Pixel Matrix Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6.1
6.1.1
These pads output the display row signals.
6.1.2
These pads output the display column signals.
6.1.3
V
6.1.4
V
multiplier. For split power supplies V
connected together. If only one supply voltage is available,
all three supplies must be connected together.
6.1.5
If, in the application, an external V
must be left open-circuit; otherwise (if the internal voltage
multiplier is enabled) the chip may be damaged. V
should not be driven when V
allowed value otherwise a low impedance path between
V
6.1.6
This is the V
If the internal V
V
driven when V
otherwise a low impedance path between V
will exist.
6.1.7
This is the input to the internal voltage multiplier regulator.
It must be connected to V
generator is used otherwise it may be left open-circuit.
V
minimum allowed value, otherwise a low impedance path
between V
6.1.8
I
6.1.9
SDAOUT is the serial data acknowledge for the I
By connecting SDAOUT to SDA externally, the SDA line
becomes fully I
2001 Nov 07
2
SS1
DD1
LCDOUT
LCDIN
LCDSENSE
C-bus serial data input.
65
and V
is the logic supply. V
Pin functions
must be connected together. V
R0
C0
V
V
V
V
V
SDA
SDAOUT
and V
133 pixel matrix driver
SS1
DD1
LCDOUT
LCDIN
LCDSENSE
LCDSENCE
SS2
should not be driven when V
LCD
TO
TO
AND
DD1
TO
SS1
must be connected together.
2
LCD
R64
C132
C-bus compatible. Having the
supply for when an external V
V
is below its minimum allowed value,
V
will exist.
DD3
generator is used, then V
SS2
and V
LCDOUT
DD2
SS1
DD1
and V
will exist.
when the internal voltage
is below its minimum
LCD
DD3
DD2
LCDIN
is used, V
are for the voltage
and V
DD1
LCDIN
should not be
is below its
LCDOUT
DD3
LCD
LCDOUT
and V
2
must be
is used.
C-bus.
LCDOUT
and
SS1
7
acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8535
will not be able to create a valid LOW level. By splitting the
SDA input from the SDAOUT output the device could be
used in a mode that ignores the acknowledge bit. In COG
applications where the acknowledge cycle is required or
where read back is required, it is necessary to minimize
the track resistance from the SDAOUT pad to the system
SDA line to guarantee a valid LOW level.
6.1.10
I
6.1.11
Least significant bits of the I
Table 1 Slave address
The slave address is a concatenation of the following bits
0, 1, 1, 1, 1, SA1, SA0 and R/W.
6.1.12
If the on-chip oscillator is used this input must be
connected to V
6.1.13
When the external reset input is LOW the chip will be reset
(see Section 7.1). If an external reset is not required, this
pad must be tied to V
in Chapter 12.
6.1.14
In applications T4 and T5 must be connected to V
T1, T2 and T3 are to be left open-circuit.
2
SA1 AND SA0
C-bus serial clock input.
0 and 0
0 and 1
1 and 0
1 and 1
SCL
SA0
OSC
RES
T1, T2, T3, T4
AND
DD1
SA1
or V
MODE
DD1
write
write
write
write
read
read
read
read
SS1
AND
. Timing for the RES pad is given
.
2
T5
C-bus slave address.
SLAVE ADDRESS
Product specification
PCF8535
7CH
7DH
7AH
7BH
7EH
7FH
78H
79H
SS
.