pcf8535 NXP Semiconductors, pcf8535 Datasheet - Page 30

• Manufacturer Part Number: pcf8535
• Description: 65 X 133 Pixel Matrix Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.17
7.17.1
The I
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
7.17.1.1
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
Bit transfer is illustrated in Fig.21.
7.17.1.2
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line, while the clock
is HIGH, is defined as the STOP condition (P). The
START and STOP conditions are illustrated in Fig.22.
7.17.1.3
The system configuration is illustrated in Fig.23:
2001 Nov 07
handbook, full pagewidth
Transmitter: the device which sends the data to the bus
Receiver: the device which receives the data from the
bus
65
2
C-bus is for bidirectional, two-line communication
I
2
C-bus interface
C
133 pixel matrix driver
HARACTERISTICS OF THE
Bit transfer
START and STOP conditions
System configuration
SDA
SCL
I
2
C-
BUS
data valid
data line
stable;
Fig.21 Bit transfer.
30
allowed
change
of data
7.17.1.4
Each byte of 8 bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH signal put on the bus by
the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I
in Fig.24.
Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.
Acknowledge
MBC621
Product specification
2
C-bus is illustrated
PCF8535