pcf8535 NXP Semiconductors, pcf8535 Datasheet - Page 27

• Manufacturer Part Number: pcf8535
• Description: 65 X 133 Pixel Matrix Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.16.5
7.16.5.1
DM
Direct mode allows V
V
used for V
DOF
Display off will turn off all internal analog circuitry that is not
required for temperature measurement.
As a consequence the display will be turned off. This
mode is only required if temperature measurements are
required whilst in Power-down mode.
7.16.5.2
The internal oscillator may be disabled and the source
clock for the display is derived from the OSC pad. It is
important to remember that LCDs are damaged by DC
7.16.6
Table 16 Instruction set
2001 Nov 07
H[2:0] = XXX; RAM read/write command page
Write data
Read status
NOP
Default H[2:0]
H[2:0] = 111; function and RAM command page
Command page
Function set
RAM page
Set Y address of
RAM
Set X address of
RAM
H[2:0] = 110; display setting command page
Display control
External display
control
Bias system
DD2
INSTRUCTION
65
. This may be useful in systems where V
S
I
NSTRUCTION SET
133 pixel matrix driver
LCD
PECIAL FEATURE COMMAND PAGE
State control
Oscillator setting
.
LCDOUT
D/C
1
0
0
0
0
0
0
0
0
0
0
0
R/W
to be sourced directly from
0
1
0
0
0
0
0
0
0
0
0
0
(1)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D
D
0
0
0
0
0
0
1
0
0
0
7
7
D
D
X
0
0
0
0
0
1
0
0
0
DD
6
6
6
I
is to be
2
C-BUS COMMAND BYTE
D
D
X
0
0
0
0
1
0
0
0
0
5
5
5
D
D
X
27
0
0
0
1
0
0
0
0
1
4
4
4
voltages and that the clock, whether derived internally or
externally, should never be disabled whilst the display is
active. The internal oscillator is switched off during
power-down mode.
Using an external clock and disabling it during
power-down mode will further reduce the standby current.
If it is not possible to disable it externally, then it is worth
noting that by selecting the internal clock, which is disabled
during power-down mode, the same effect may be
achieved.
7.16.5.3
The chip may be mounted on either a glass, foil or tape
carrier package. For these applications, different
organizations of the row pads are required to negate the
necessity of routing tracks under the device. The
TRS and BRS allow for this swapping. The behaviour of
both of these bits is further described in Section 7.15.
D
D
Y
X
0
0
1
0
0
0
1
0
3
3
3
3
XM
BS
MX
PD
D
D
H
Y
X
0
0
1
COG/TCP
2
2
2
2
2
2
0
BS
MY
D
D
H
Y
X
V
D
0
0
0
1
1
1
1
1
1
BS
D
D
H
Y
X
0
0
E
0
0
1
0
0
0
0
0
0
write data to display RAM
return result of temperature
measurement
no operation
jump to H[2:0] = 111
select command page
power-down control, data
entry mode
set RAM page for X address
set Y address of RAM
0
set X address of RAM
0
set display mode
mirror X, mirror Y
set bias system
I
2
Y
X
C-BUS COMMANDS
8
127
Product specification
PCF8535