adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 21

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

Functional Description
The ADC12EU050 employs a number of unique strategies to
provide a high performance multi-channel ADC that offers a
significant power consumption reduction when compared to
compteting architectures, as well as easing system level de-
sign. The ultra-low power performance of the ADC12EU050
is derived from the implementation of a fast continuous time
sigma delta (CT
nology are:
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•
•
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The major signal path blocks are: clipping control; CT
modulator; digital decimation filter; 12 bit serializer; and finally
the LVDS/SLVS outputs. The PLL is critical to the operation
of the ADC12EU050, and the PLL also provides the bit and
word clock outputs. The SPI Control Interface gives uncom-
plicated user access to the ADC registers.
1.0 12-BIT SIGMA DELTA ADC CORE
The ADC12EU050 comprises eight analog ADC channels
using a CT
performance with ultra-low power, while operating from a
minimal 1.2V supply.
The CT
modulator operating at a nominal 16 times over-sampling rate
in combination with a 3-bit quantizer. The modulator output is
coupled to a power efficient digital decimation filter that dec-
imates the high rate modulator output (640 to 800MHz) to
provide output data at a sample rate between 40 MSPS and
50 MSPS.
A benefit of the CT
external anti-alias filters for most applications. This benefit is
derived from a combination of the design of the analog sigma
delta modulator and digital decimation filter. The digital filter
achieves a steep transition band, and provides 72 dB of at-
tenuation in the stop band. Using the digital equalizer, the
signal transfer characteristics including phase performance
can be optimized so as to minimise group delay variation. In
applications where it is not required, the digital equalizer can
be disabled to further save power.
1.1 DIFFERENTIAL INPUT STAGE
The ADC can capture high speed analog signals without re-
sorting to a complex fast sample-and-hold amplifier (SHA) as
used in pipeline ADCs. This is where CT
rives much of its power and performance benefits. This fea-
ture also assists external circuit design. In the case of the SHA
inputs of pipeline ADCs, the effective input capacitance is
time variant, requiring a powerful input buffer to drive to the
resolution limits of the system. The input stage of the ADC is
purely resistive (1.3kΩ single ended) driving into virtual earth.
As a result the ADC12EU050 is extremely easy to drive as its
input impedance is not complex. It also means that external
lower power input buffering circuitry can used, and can be
completely eliminated in some cases.
Intrinsic anti-alias filter – the digital decimating filter
provides an intrinsic anti-alias filter, eliminating external
analog filter components, and simplifying multi-channel
designs.
Instant overload recovery (IOR) system guarantees
extremely fast recovery from overload (<1ps), and no
settling errors on return from overload.
Ultra-low inter-channel crosstalk.
Digital Equalizer provides low group delay and hence
minimizes signal path delay variation.
∑
Δ ADC architecture uses a third order sigma delta
∑
Δ architecture, which provides very high dynamic
∑
Δ) modulator. Other features of this tech-
∑
Δ design is that the ADC requires no
∑
Δ technology de-
∑
Δ
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1.2 INSTANT OVERLOAD RECOVERY
The ADC12EU050 features an overload handling system
which provides instantaneous recovery from signals driving
the ADC inputs beyond the full-scale input range. The ADC
can operate in two different modes. In the default ADC mode
(IOR mode off) a full-scale input range of 2.10 V
ported, here the ADC operates with some inherent overload
recovery time, similar to a conventional ADC.
In the IOR mode, the ADC has a reduced 1.56 V
input range, but provides a significant benefit in that the ADC
can now be driven by input voltages as high as 5 dB beyond
the nominal full-scale (f
recover instantaneously. In a number of applications this fea-
ture can help simplify input stage design and manufacturing
set-up and calibration. The ADC12EU050 recovers immedi-
ately from overload with no missing codes and no settling
time.
The proprietary strategy used within the ADC12EU050 uses
high speed patented clamp techniques to limit the input signal
and keep it within the stable input range of the ADC. This
process happens at a speed equivalent to the on-chip over-
sampling rate of 640 to 800 MHz. The advantage of this
system is that it responds immediately to out of range signals.
While the inputs are over-range the ADC outputs a full scale
result. As the over-range input is removed the ADC adjusts to
the input signal level and is able to provide sampled data in-
stantaneously. The ADC’s behaviour on emerging from over-
load is repeatable and independent of whether the input
signal was positive or negative going at the point of overload.
The diagram below shows a 5dB overloaded input (2.75 V
versus 1.56 V
FIGURE 6. Continuous Time Sigma Delta Input Stage
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FIGURE 5. SHA Input Stage
Full scale), with 240,000 sample periods
IN
< 12MHz), that is 2.75 V
www.national.com
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full scale
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