adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 28

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
2.6 USING IOR MODE
As discussed in the Functional Description, IOR mode pro-
vides instantaneous recovery from overload conditions, with
FIGURE 18. Output Driver Circuit: SLVS
FIGURE 19. LVDS Training Select operation
30051127
28
As well as the different output modes, the output drive current
can also be controlled via the LVDS Control Register. The
default output drive current is 2.5mA, but this can be in-
creased to 3.5mA or 5mA, depending on output trace routing
and receiver requirements. Power consumption of the AD-
C12EU050 will increase slightly as the output driver current
is increased.
Termination
The final control feature available in the LVDS Control Reg-
ister is the choice between internal and external 100Ω termi-
nation. Although the termination is recommended to be as
close to the receiver as possible, in some cases it may be
necessary or desirable to perform this termination at the
transmitter. Internal 100Ω termination at the transmitter (the
ADC12EU050) is enabled by setting the bit TX_term to 1.
LVDS Output Training Sequences
Often it is necessary to calibrate the LVDS receiver, for ex-
ample an FPGA or DSP, so that skew between the eight ADC
output channels is minimized. In order to simplify this process,
the ADC12EU050 provides three LVDS training modes,
where a pre-defined or custom pattern is output on all eight
channels simultaneously. While a training mode is active, the
word and bit clocks are output as usual. In order to select a
training mode, the TSEL bits of the Decimator Control Reg-
ister (16h) must be programmed via the SPI interface.
There are two pre-defined training patterns, or a custom pat-
tern can be loaded via the SPI into the Serializer Custom
Pattern 0 and 1 Registers (10h and 12h). In order to return to
normal ADC operation after skew calibration, the TSEL bits
should be returned to their default value of 00.
no ringing and correct data output as soon as the input returns
in range.
Standard Use of IOR Mode
30051164