adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 25

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

On the input clock, excessive RMS jitter within the PLL band-
width will be seen in the output spectrum as sidebands, or
close in phase noise, around the fundamental signal.
Input Clock Selection
For systems which do not have a requirement for a high per-
formance clock, any standard product 40MHz – 50MHz crys-
tal oscillator will allow the ADC12EU050 to perform to
specifications. If the system requires high performance clocks
for other system components, then National Semiconductor's
LMK family of clock conditioners are recommended.
Output Clock Synchronization Across Multiple Chips
In systems containing more than one ADC12EU050, it is often
required that the timing of output samples is synchronized
across the multiple chips. The PLL in the ADC12EU050 takes
care of this automatically by aligning the output clocks with
the input clock. The user must ensure, using correct board
layout and clock buffering techniques, that the input clock to
Single Ended Input Configurations
In cost sensitive applications, a single ended input may pro-
vide adequate performance, however ADC performance will
degrade slightly. When using single ended inputs, the maxi-
FIGURE 13. Transformer Coupled Input
25
each ADC12EU050 is synchronized. If this is the case, then
the output frame clocks will also be synchronized. This means
that output samples are aligned.
2.4 ADC INPUT CONSIDERATIONS
The ADC12EU050’s sigma delta architecture offers many
flexible options for connecting input signals.
In order to obtain maximum performance from the device, it
is recommended to use a differential input connection. The
device, however, also supports single ended analog input.
Differential Input Configurations
The ADC12EU050 can be driven either actively or passively.
Transformer coupling provides another possibility for con-
verting a single ended signal into a differential signal. The
diagram below shows a transformer coupled input configura-
tion.
mum input voltage allowed is 3dB less than the 2.10V full
scale input. The diagram below shows a single ended input
configuration.
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