adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 43

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

Decimator Control Register
Address:
Attributes
Description
Default
Bit
7:5
1:0
4
3
2
b[7]
0
Reserved. Write as zero for future compatibility.
EQON: Equalizer Enable. This bit is used to enable or disable the digital equalizer. The equalizer can
be switched on in order to reduce the group delay of the output data, at the cost of increased power.
DFS: Data Format Select. Selects the format, either Offset Binary or Twos Complement of the output
data
MSB: Select the bit order of the LVDS output data stream
TSEL[1:0]: Training Sequence Select. These bits select the LVDS output data.
The default mode of operation is where the filter output data is serialized.
In the remaining modes the selected training sequence is repeatedly output from the serializer this
allows the receiving data capture circuitry to perform the de-skewing process.
One of three known words can be selected, the first two words are hard-coded in the block, the third
one, the custom pattern, is written into User Registers 10h and 12h the Serializer Custom Pattern
Registers.
Note. The outputs bit-clock and word-clock are not affected by the value of the Training Sequence
Select bits.
Reserved
b[6]
00
01
10
11
0
1
0
1
0
1
0
16h
Write Only.
Register 17h reads back contents of register 16h.
Equalizer disabled
Equalizer enabled
2s Complement
Offset Binary
LSB first
MSB first
ADC data[11:0]
Training sequence 1: 000000111111
Training sequence 2: 101010101010
Training sequence 3: custom pattern
b[5]
0
EQON
b[4]
0
43
DFS
b[3]
0
Description
MSB
b[2]
0
b[1]
0
TSEL[1:0]
b[0]
0
www.national.com
HEX
00 h