adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 24

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
2.0 POWER-UP SEQUENCE
The ADC12EU050 has three separate power supplies: Ana-
log (V
ADC contains a power on reset circuit, connected to VA, and
so to ensure correct reset of both analog and digital logic of
the ADC, the power supplies should be provided in the fol-
lowing order:
1.
2.
3.
If this order is not followed, then the user should issue a reset
via the reset pin (RST) immediately after power up.
Additionally, it is required that the rise time for each voltage
supply is longer than the minimum rise time stated in the
Electrical Specifications section of this data sheet.
There is no required sequence for powering down the ADC.
2.1 ADC START-UP SEQUENCE
After any reset, either power-on reset, software reset via SPI
or hardware reset via the RST pin, the chip undergoes a se-
ries of internal calibrations and the PLL/VCO will lock to the
external clock.
After reset, the ADC12EU050’s registers have the default val-
ues shown in register tables. The registers can be pro-
grammed via the SPI after reset, even during the period while
the chip is performing the internal calibrations mentioned in
the previous paragraph.
During reset and until the PLL is locked, the LVDS outputs will
not provide valid data. Furthermore, the ADC has an inherent
data conversion latency, which is related to the pipeline
stages of the digital decimating filter. Until the data conversion
latency has passed, the data outputs will be invalid.
Thus the maximum time until valid sampled data is received
at the outputs is:
Specific values for these times can be found in the Electrical
Specifications section of this datasheet.
2.2 USING ADC LOW POWER MODES
As explained previously in the Functional Description, the
ADC12EU050 offers several power management modes.
Sleep mode offers the fastest wake-up time, and should be
used in applications where duty cycle powering of the ADC is
required. In this case it is recommended to toggle sleep mode
via the SLEEP pin, which will give a faster cycle time than
programming the SLEEP bit through the SPI, due to the extra
time required to send a command through the SPI port.
The Power Down mode is accessible via the SPI port. Due to
the power-up time of the ADC coupled with the programming
time of the SPI port, this mode should be used to power the
chip down for longer time periods.
Channel power down allows one or more channels to be
turned off independently, with the corresponding power sav-
ing.
2.3 CLOCK SELECTION CONSIDERATIONS
The ADC12EU050 has an on-chip PLL, which simplifies the
task of clock source selection and clock network design.
Clock Input Connection
The ADC is designed to accept either single ended or differ-
ential clock inputs. Furthermore, the clock source can be a
sine or square wave. In order to obtain the best performance,
V
V
V
PLL lock time + ADC Latency
A
DR
D
A
), Digital (V
D
) and the output drive voltage ( V
DR
). The
24
a differential square wave clock should be used. When using
a differential clock, the clock traces should be routed as
100Ω differential pairs, and terminated with a 100Ω resistor
close to the chip. A single ended clock input should be con-
nected to pin 47 (CLK+/SE), and pin 48 (CLK-) should be
grounded.
On-chip PLL
The benefit of having an on chip PLL is that in most applica-
tions a high precision clock source is not required. The exter-
nal clock's contribution to aperture jitter is reduced dramati-
cally by the jitter clean-up properties of the PLL, which
ensures that any RMS jitter outside of the PLL bandwidth is
attenuated. The PLL also significantly relaxes the input clock
duty cycle requirements, accepting input clock duty cycles of
20% to 80%.
The PLL offers two choices of bandwidth. For the majority of
systems, the default bandwidth of 400kHz is suitable. If the
system already contains a high performance clock, with ex-
cellent RMS jitter performance up to a 1.4MHz bandwidth,
then the PLL’s high bandwidth mode may be used.
FIGURE 11. PLL Phase Noise Transfer Function: f
FIGURE 12. PLL Phase Noise Transfer Function: f
40MHz
50MHz
30051115
30051116
s
s
=
=