adc12eu050eb National Semiconductor Corporation, adc12eu050eb Datasheet - Page 35

• Manufacturer Part Number: adc12eu050eb
• Description: Adc12eu050 Ultra-low Power, Octal, 12-bit, 40-50 Msps Sigma-delta Analog-to-digital Converter
• Manufacturer: National Semiconductor Corporation

Top Control Register
The Top Control Register is the basic initialization and control register for the device.
Address:
Attributes
Description
Default
Bit
7:6
5
4
3
2
1
0
Reserved. Write as zero for future compatibility.
CBR: Control Bus Read. When asserted register 00h (this register) can be read, but no other registers.
When de-asserted all other registers can be read, but not register 00h.
0
1
40/50: Selects the ADC sample rate. This bit should be set according to the applied input clock to obtain
optimal performance.
0
1
SRES: Software Reset. When asserted the software reset will reset the whole device. SRES performs
the same function as the hardware reset (RST pin).
The SRES is self clearing in approximately 2µs.
0
1
SPIOD: SPI Open Drain mode.
0
1
SLEEP: Sleep Mode. Powers down the device with the exception of the PLL and the reference blocks.
The time to wake-up from sleep mode is < 10µs.
0
1
PD: Power Down Mode. Completely powers down the device. The power up time is approximately
20ms.
0
1
b[7]
0
Reserved
00h
Write Only.
Register 01h reads back contents of register 00h, if CBR is set.
Register 00h cannot be read from address 01h. All other registers can be read back.
Register 00h can be read from address 01h. All other registers cannot be read back.
45-50MSPS
40-45MSPS
Software Reset Inactive
Software Reset Active
Digital Logic Output
Open Drain Mode. Enables SPI Driver to operate above V
Sleep Mode Inactive
Sleep Mode Active
PD Mode Inactive, device operates normally
PD Mode Active, device powered down
b[6]
0
CBR
b[5]
0
40/50
b[4]
35
0
Description
SRES
b[3]
0
SPIOD
b[2]
0
DR
SLEEP
b[1]
0
b[0]
PD
0
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