atf280e ATMEL Corporation, atf280e Datasheet - Page 12

• Manufacturer Part Number: atf280e
• Description: Rad Hard Reprogrammable Fpga
• Manufacturer: ATMEL Corporation

tion SRAM. The D1:D15 pins will transition from the user programmed state to CMOS inputs
with nominal 20K internal pull-up resistors as the SRAM at those locations is cleared by the con-
figuration clear cycle.
When in Modes 2 or 6, D1:D7 become inputs during configuration download. D1:D7 are not
used in the serial Modes 0, 1 and 7.
When in Modes 2 or 6, D8:D15 become optional inputs during configuration download. They
become available as soon as the appropriate bit in the configuration control register is set.
D8:D15 are not used in the serial Modes 0, 1 and 7.
A0:A19 - Configuration Address Bus (Input/Output)
A0:A19(1) are used to control external addressing of memories during downloads. During
power-on-reset or manual reset, A0:A19 are controlled by the configuration SRAM. The A0:A19
pins will transition from the user programmed state to CMOS inputs with nominal 20K internal
pull-up resistors as the SRAM at those locations is cleared by the configuration clear cycle.
When in Mode 6, A0:A19 become outputs during configuration download. A0:A19 are used only
in Mode 6.
Note: 1. Pin A2 is also pin CS1, which is available only for Mode 2. See the description for CS1
on page 5 for more details.
CS0/CS1 - Configuration Chip Select (Input/Output)
CS0 is an FPGA configuration chip select. It is active Low. During power-on-reset or manual
reset, CS0 is controlled by the configuration SRAM. The CS0 pin will transition from the user
programmed state to a CMOS input with a nominal 20K internal pull-up resistor as the SRAM at
that location is cleared by the configuration clear cycle. In Mode 1, it is used as a chip select to
enable configuration to begin. It is most often used as the chip select of the downstream device
in a cascade chain, and is usually driven by CSOUT of the upstream device. Releasing CS0 dur-
ing configuration causes the Mode 1 FPGA to abort the download and release CON.
CS0 is used only in Mode 1. CS1 is used only in Mode 2
Note: 1. Pin CS1 is also pin A2, which is active only for Mode 6. See the description for A0:A19,
on page 5 for more details.
CSOUT - Configuration Cascade Output (Output)
CSOUT is the configuration pin used to enable the downstream device in a cascade chain. Dur-
ing power-on-reset or manual reset, CSOUT is controlled by the configuration SRAM. The
CSOUT pin will transition from the user programmed state to a CMOS input with a nominal 20K
internal pull-up resistor as the SRAM at that location is cleared by the configuration clear cycle.
During configuration download, CSOUT becomes an optional output. It is enabled by default
after reset, and may be enabled or disabled via the configuration control register. If the user has
disabled the cascade function, the pin remains a user I/O. If the cascade function is enabled, the
CSOUT pin is driven High at the start of configuration download. At the end of the device’s por-
tion of the cascade bitstream, the CSOUT pin is driven Low (and into the CS0 or CS1 of the
downstream device) to enable the downstream device. CSOUT is released by the device at the
end of the cascade bitstream and becomes a fully functional user I/O.
CHECK - Configuration Check (Input/Output)
CHECK is a configuration control pin used to control the Check Function. The Check Function
takes a bitstream and compares it to the contents of a previously loaded bitstream and notifies
the user of any differences. Any differences causes the INIT pin to go Low. During power-on-
ATF280E
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7750A–AERO–07/07