atf280e ATMEL Corporation, atf280e Datasheet - Page 17

• Manufacturer Part Number: atf280e
• Description: Rad Hard Reprogrammable Fpga
• Manufacturer: ATMEL Corporation

4.2.1
4.2.2
4.2.3
4.2.4
7750A–AERO–07/07
Synthesis Mode
Arithmetic Mode
DSP/Multiplier Mode
Counter Mode
This mode is particularly important for the use of VHDL design. VHDL Synthesis tools generally
will produce as their output large amounts of random logic functions. Having a 4-input LUT struc-
ture gives efficient random logic optimization without the delays associated with larger LUT
structures. The output of any cell may be registered, tri-stated and/or fed back into a core cell.
Figure 4-4.
This mode is frequently used in many designs. As can be seen in the figure, the ATF280E core
cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core
cell. Note that the sum output in this diagram is registered. This output could then be tri-stated
and/or fed back into the cell.
Figure 4-5.
This mode is used to efficiently implement array multipliers. An array multiplier is an array of bit-
wise multipliers, each implemented as a full adder with an upstream AND gate. Using this AND
gate and the diagonal interconnects between cells, the array multiplier structure fits very well
into the ATF280E architecture.
Figure 4-6.
Counters are fundamental to almost all digital designs. They are the basis of state machines,
timing chains and clock dividers. A counter is essentially an increment by one function (i.e., an
adder), with the input being an output (or a decode of an output) from the previous stage. A 1-bit
Synthesis Modes
Arithmetic Mode
DSP/Multiplier Mode
ATF280E
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