atf280e ATMEL Corporation, atf280e Datasheet - Page 26
atf280e
Manufacturer Part Number
atf280e
Description
Rad Hard Reprogrammable Fpga
Manufacturer
ATMEL Corporation
Datasheet
1.ATF280E.pdf
(45 pages)
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6.1
6.2
26
Global Clocks
Fast Clocks
ATF280E
Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global
Clock pins. Any clocks used in the design should use global clocks where possible. These sig-
nals are distributed across the top edge of the FPGA along special high-speed buses. Global
Clock signals can be distributed throughout the FPGA with less than 1 ns skew.
This can be done by using Assign Pin Locks command in the IDS software to lock the clocks to
the Global Clock locations.
There are four Fast Clocks (FCK1 - FCK4) on the ATF280E, two per edge column of the array
for PCI specification. Even the derived clocks can be routed through the Global network. Access
points are provided in the corners of the array to route the derived clocks into the global clock
network.
The IDS software tools handle derived clocks to global clock connections automatically if used.
7750A–AERO–07/07
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