atf280e ATMEL Corporation, atf280e Datasheet - Page 25

• Manufacturer Part Number: atf280e
• Description: Rad Hard Reprogrammable Fpga
• Manufacturer: ATMEL Corporation

6. Clocking Scheme
7750A–AERO–07/07
The entire ATF280E clocking scheme (including clock trees and muxes) is SET hardened.
There are eight differential Global Clock buses (GCK1 - GCK8) on the ATF280E FPGA. In addi-
tion to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4).
Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Column
Clock mux is at the top of every column of an array and the Sector Clock mux is at every four
cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock
provided to each sector column of four cells is inverted, non-inverted or tied off to “0”, using the
Sector Clock mux to minimize the power consumption in a sector that has no clocks.
The clock can either come from the Column Clock or from the Plane 4 express bus. The
extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast
clocking to left-side I/Os. The extreme-right Column Clock mux has two additional inputs as well,
FCK3 and FCK4, to provide fast clocking to right-side I/Os.
The register in each cell is triggered on a rising clock edge by default. Before configuration at
power-up, constant “0” is provided to each register’s clock pins. After configuration at power-up,
the registers either set or reset, depending on the user’s choice. The clocking scheme is
designed to allow efficient use of multiple clocks with low clock skew, both within a column and
across the core cell array.
Figure 6-1.
Clocking (for One Column of Cells)
ATF280E
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