atf280e ATMEL Corporation, atf280e Datasheet - Page 23

• Manufacturer Part Number: atf280e
• Description: Rad Hard Reprogrammable Fpga
• Manufacturer: ATMEL Corporation

ATF280E
Reading and writing of the 10ns 32 x 4 dual-port FreeRAM are independent of each other. Read-
ing the 32 x 4 dual-port RAM is completely asynchronous.
Latches on Write Address, Write Enable and Data In are transparent: when Load is logic 1, data
flows through, when Load is logic 0, data is latched. These latches are used to synchronize
Write Address, Write Enable Not, and Din signals for a synchronous RAM.
Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the
memory latch together form an edge-triggered flip flop. When a nibble is (Write) addressed and
LOAD is logic 1 and WE is logic 0, data flows through the bit. When a nibble is not (Write)
addressed or LOAD is logic 0 or WE is logic 1, data is latched in the nibble.
The two CLOCK muxes are controlled together; they both select CLOCK (for a synchronous
RAM) or they both select “1” (for an asynchronous RAM). CLOCK is obtained from the clock for
the sector-column immediately to the left and immediately above the RAM block.
Writing any value to the RAM clear byte during configuration clears the RAM (see the
“AT40K/40KAL Configuration Series” application note at www.atmel.com).
Figure 5-2.
RAM Logic
Note:
Ain and Aout are 5 bits wide, and the memory block is 32x4.
Here is an example of a RAM macro constructed using ATF280E’s FreeRAM cells. The macro
shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic
required to complete the address decoding for the macro. Most of the logic cells in the sectors
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