ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 12

• Manufacturer Part Number: ep1c6t144i8es
• Description: Cyclone Fpga Family
• Manufacturer: Altera Corporation

Cyclone FPGA Family Data Sheet
Figure 6. LE in Normal Mode
Note to
(1)
12
addnsub (LAB Wide)
data1
data2
data3
cin (from cout
of previous LE)
data4
This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
Figure
(1)
6:
Register Feedback
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see
Quartus II Compiler automatically selects the carry-in or the data3 signal
as one of the inputs to the LUT. Each LE can use LUT chain connections to
drive its combinatorial output directly to the next LE in the LAB.
Asynchronous load data for the register comes from the data3 input of
the LE. LEs in normal mode support packed registers.
4-Input
LUT
Register chain
connection
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
sclear
(LAB Wide)
ADATA
ENA
D
ALD/PRE
aload
CLRN
Q
Preliminary Information
Figure
Altera Corporation
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register
chain output
6). The