ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 27

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ep1c6t144i8es

Manufacturer Part Number
ep1c6t144i8es
Description
Cyclone Fpga Family
Manufacturer
Altera Corporation
Datasheet
Preliminary Information
Altera Corporation
4K
2K
1K
512
256
128
512
256
128
4K
2K
1K
512
256
512
256
Table 6. M4K RAM Block Configurations (Simple Dual-Port)
Table 7. M4K RAM Block Configurations (True Dual-Port)
Read Port
1
2
4
1
2
4
8
16
32
9
18
36
8
16
9
18
Port A
4K
v
v
v
v
v
v
1
4K
Memory Configuration Sizes
The memory address depths and output widths can be configured as
4,096 1, 2,048 2, 1,024 4, 512 8 (or 512 9 bits), 256 16 (or 256
bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration
is not available in the true dual-port mode. Mixed-width configurations
are also possible, allowing different read and write widths.
summarize the possible M4K RAM block configurations.
When the M4K RAM block is configured as a shift register block, the
designer can create a shift register up to 4,608 bits (w
2K
v
v
v
v
v
v
v
v
v
v
v
1
2
2K
1K
v
v
v
v
v
v
v
v
v
v
v
2
4
512 8 256 16 128 32 512 9 256 18 128 36
1K
v
v
v
v
v
v
v
v
v
v
v
4
Write Port
v
v
v
v
v
v
512 8
Port B
v
v
v
v
v
v
v
v
v
v
v
Cyclone FPGA Family Data Sheet
256 16
v
v
v
v
v
v
v
v
512 9
m n).
v
v
v
v
v
Tables 6
256 18
v
v
and
v
v
v
18
27
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