ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 39

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ep1c6t144i8es

Manufacturer Part Number
ep1c6t144i8es
Description
Cyclone Fpga Family
Manufacturer
Altera Corporation
Datasheet
Preliminary Information
Altera Corporation
Figure 26. Cyclone PLL Global Clock Connections
Notes to
(1)
(2)
(3)
(4)
PLL1_OUT (3), (4)
PLL 1 supports one single-ended or LVDS input via pins CLK0 and CLK1.
PLL2 supports one single-ended or LVDS input via pins CLK2 and CLK3.
PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are
available as regular user I/O pins.
The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the
144-pin TQFP package does not support external clock output from PLL2.
CLK1 (1)
Figure
CLK0
26:
PLL1
g0
g1
e
G0
G1
G2
G3
G4
G5
G6
G7
g0
g1
e
Cyclone FPGA Family Data Sheet
PLL2
CLK2
CLK3 (2)
PLL2_OUT (3), (4)
39

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