ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 32

• Manufacturer Part Number: ep1c6t144i8es
• Description: Cyclone Fpga Family
• Manufacturer: Altera Corporation

Cyclone FPGA Family Data Sheet
Figure 19. Input/Output Clock Mode in Simple Dual-Port Mode
Note to
(1)
32
wraddress[ ]
address[ ]
byteena[ ]
outclken
outclock
inclken
All registers shown except the rden register have asynchronous clear ports.
inclock
data[ ]
wren
rden
Figures
6 LAB Row
Clocks
6
19:
Read/Write Clock Mode
The M4K memory blocks implement read/write clock mode for simple
dual-port memory. The designer can use up to two clocks in this mode.
The write clock controls the block’s data inputs, wraddress, and wren.
The read clock controls the data output, rdaddress, and rden. The
memory blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 20
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
shows a memory block in read/write clock mode.
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Byte Enable
Write Address
Read Enable
Write Enable
Memory Block
Note (1)
Data Out
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
512 ´ 8
D
ENA
Preliminary Information
Q
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