ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 78

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ep1c6t144i8es

Manufacturer Part Number
ep1c6t144i8es
Description
Cyclone Fpga Family
Manufacturer
Altera Corporation
Datasheet
Cyclone FPGA Family Data Sheet
78
Internal timing parameters are specified on a speed grade basis
independent of device density.
timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP
blocks, and MultiTrack interconnects.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
H
CO
LUT
CLR
PRE
CLKHL
SU
H
CO
PIN2COMBOUT_R
PIN2COMBOUT_C
COMBIN2PIN_R
COMBIN2PIN_C
CLR
PRE
CLKHL
Table 45. LE Internal Timing Microparameters
Table 46. IOE Internal Timing Microparameters
Symbol
Symbol
Min
129
129
107
Min
280
280
29
12
98
65
95
-6
-6
1,107
1,112
2,776
2,764
Max
Max
173
454
161
Tables 45
Min
Min
148
148
123
107
308
308
104
33
13
71
through
-7
-7
1,217
1,223
3,053
3,040
Max
Max
198
522
177
48
Preliminary Information
show the internal
Min
Min
167
167
139
117
336
336
114
37
15
78
Altera Corporation
-8
-8
1,328
1,334
3,331
3,316
Max
Max
224
590
193
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps

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