ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 8

• Manufacturer Part Number: ep1c6t144i8es
• Description: Cyclone Fpga Family
• Manufacturer: Altera Corporation

Cyclone FPGA Family Data Sheet
Figure 4. LAB-Wide Control Signals
8
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
6
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal will also use labclkena1. If
the LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal will turn off
the LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
With the LAB-wide addnsub control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending on
data.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack
allows clock and control signal distribution in addition to data.
shows the LAB control signal generation circuit.
labclk1
labclkena1
labclk2
labclkena2
asyncload
or labpre
TM
syncload
interconnect’s inherent low skew
labclr1
Preliminary Information
labclr2
Altera Corporation
synclr
Figure 4
addnsub