z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 165

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

150
CSI/O Transmit/Receive Register (TRDR: 0BH)
UM005003-0703
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Z8018x
Family MPU User Manual
7
Table 22.
After RESET, the CKS pin is configured as an external clock input (SS2,
SS1, SS0 = 1). Changing these values causes CKS to become an output pin
and the selected clock is output when transmit or receive operations are
enabled.
CSI/O Interrupts
The CSI/O interrupt request circuit is shown in Figure 58.
Note: ( ) indicates the baud rate (BPS) at Phi = 4 MHz.
SS2
0
0
0
0
1
1
1
1
6
CSI/O Baud Rate Selection
SS1
0
0
1
1
0
0
1
1
5
CSI/O Transmit/Receive Data
SS0
0
1
0
1
0
1
0
1
4
Divide Ratio
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External Clock input (less than
R/W
20
40
80
160
320
640
1280
0
3
2
Baud Rate
(200000)
(100000)
(50000)
(25000)
(12500)
(6250)
(3125)
1
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20)
0