z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 180

• Manufacturer Part Number: z80189
• Description: Z80180, Z8s180, Z8l180 Mpu Operation
• Manufacturer: ZiLOG Semiconductor

1.
*n = 0, 1
PRT Operation Notes
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Secondary Bus Interface
E clock Output Timing
The Z8X180 also has a secondary bus interface that allows it to easily
interface with other peripheral families.
TMDR data is accurately read without stopping down counting by
reading the lower (TMDRnL*) and higher (TMDRnH*) bytes in that
order. Also, TMDR is read or written by stopping the down
counting.
Take care to ensure that a timer reload does not occur during or
between lower (RLDRnL*) and higher (RLDRnH*) byte writes. This
may be guaranteed by system design/timing or by stopping down
counting (with TMDR containing a non-zero value) during the RLDR
updating. Similarly, in applications where TMDR is written at each
TMDR overflow, the system/software design must guarantee that
RLDR can be updated before the next overflow occurs. Otherwise,
time base inaccuracy occurs.
During RESET, the multiplexed A18/TOUT pin reverts to the address
output. By reprogramming the TOC1 and TOC0 bits, the timer output
function for PRT channel 1 is selected. The following paragraph
describes the initial state of the TOUT pin after TOC1 and TOC0 are
programmed to select the PRT channel 1 timer output function.
PRT (channel 1) has not counted down to 0.
If the PRT has not counted down to 0 (timed out), the initial state of
TOUT depends on the programmed value in TOC1 and TOC0.
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Family MPU User Manual
UM005003-0703
Z8018x
165