z80189 ZiLOG Semiconductor, z80189 Datasheet - Page 317
z80189
Manufacturer Part Number
z80189
Description
Z80180, Z8s180, Z8l180 Mpu Operation
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z80189.pdf
(326 pages)
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Register
DMA/WAIT Control
Register:
Table 57.
DCNTL
Mnemonics Address
Internal I/O Registers (Continued)
3
2
during RESET
R/W
bit
MWI1,0
DIM1,0
DMSi
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
0
MWI1
R/W
1
The number of
wait states
Transfer Mode
Edge sense
Level sense
Sense
M®I/O
M®I/O
I/O®M
I/O®M
0
1
2
3
Family MPU User Manual
MWI0
R/W
Memory Wait Insertion
1
Remarks
IWI1
R/W
1
Address Increment/Decrement
MAR1+1
MAR1-1
IAR1 fixed
IAR1 fixed
IWI0
R/W
IWI1,0
I/O Wait Insertion
1
0 0
0 1
1 0
1 1
IAR1 fixed
IAR1 fixed
MAR1+1
MAR1-1
DMS1
R/W
0
UM005003-0703
The number of
wait states
0
2
3
4
DMS0
0
R/W
DREQi Select, i=1,0
Z8018x
DIMA1 DIMA0
R/W
0
R/W
DMA Ch 1
I/O Memory
Mode Select
0
301
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