mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 137

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

9.3 SIM Bus Clock Control and Generation
9.3.1 Bus Timing
9.3.2 Clock Startup from POR or LVI Reset
MC68HC908AS60 — Rev. 1.0
OSC1
PLL
CGMVCLK
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
from either an external oscillator or from the on-chip phase-locked loop
(PLL). See
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after 4096 CGMXCLK cycles.
The RST pin is driven low by the SIM during this entire period. The bus
clocks start upon completion of the timeout.
MONITOR MODE
CIRCUIT
Freescale Semiconductor, Inc.
SELECT
CLOCK
USER MODE
BCS
For More Information On This Product,
CGM
PTC3
Figure 9-3. CGM Clock Signals
System Integration Module (SIM)
Section 10. Clock Generator Module
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2
A
B S*
Section 10. Clock Generator Module
*When S = 1,
CGMOUT = B
CGMXCLK
CGMOUT
SIM Bus Clock Control and Generation
Figure
System Integration Module (SIM)
9-3. This clock can come
SIM COUNTER
2
SIM
(CGM).
GENERATORS
BUS CLOCK
Technical Data
(CGM).