mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 143

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

9.5.2 SIM Counter During Stop Mode Recovery
9.5.3 SIM Counter and Reset States
9.6 Program Exception Control
9.6.1 Interrupts
MC68HC908AS60 — Rev. 1.0
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
CONFIG-1 register. If the SSREC bit is a logic 1, then the stop recovery
is reduced from the normal delay of 4096 CGMXCLK cycles down to
32 CGMXCLK cycles. This is ideal for applications using canned
oscillators that do not require long startup times from stop mode.
External crystal applications should use the full stop recovery time, that
is, with SSREC cleared.
External reset has no effect on the SIM counter (see
for details). The SIM counter is free-running after all reset states. See
9.4.2 Active Resets from Internal Sources
internal reset recovery sequences.
Normal, sequential program execution can be changed in three different
ways:
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 9-9
1. Interrupts:
2. Reset
3. Break interrupts
Freescale Semiconductor, Inc.
For More Information On This Product,
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
System Integration Module (SIM)
shows interrupt recovery timing.
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Figure 9-8
shows interrupt entry timing.
System Integration Module (SIM)
for counter control and
Program Exception Control
9.7.2 Stop Mode
Technical Data