mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 349

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

21.5.4.10 Valid SOF Symbol
21.5.4.11 Valid BREAK Symbol
21.5.5 Message Arbitration
MC68HC908AS60 — Rev. 1.0
Message arbitration on the J1850 bus is accomplished in a
non-destructive manner, allowing the message with the highest priority
to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it waits until the bus is idle. However, if
multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF
symbol and continue with each bit thereafter. If a write to the BDR (for
instance, to initiate transmission) occurred on or before
ACTIVE
PASSIVE
In
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid SOF symbol.
In
not occur until after e, the current symbol will be considered a valid
BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be
transmitted onto the J1850 bus. See
BDLC response to BREAK symbols.
Freescale Semiconductor, Inc.
Figure 21-11. J1850 VPW Received BREAK Symbol Times
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Figure
Figure 21-10
Byte Data Link Controller-Digital (BDLC-D)
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21-11, if the next active-to-passive received transition does
240 s
(4), if the active-to-passive received transition
Byte Data Link Controller-Digital (BDLC-D)
21.5.2 J1850 Frame Format
e
BDLC MUX Interface
(2) VALID BREAK SYMBOL
Technical Data
for