mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 150

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
Technical Data
CGMXCLK
INT/BREAK
IAB
NOTE:
Figure 9-16. Stop Mode Recovery from Interrupt or Break
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the configuration
register (CONFIG-1). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
Freescale Semiconductor, Inc.
CPUSTOP
STOP +1
Note: Previous data can be operand data or the STOP opcode, depending on the last
For More Information On This Product,
R/W
IAB
IDB
instruction
System Integration Module (SIM)
Go to: www.freescale.com
STOP ADDR
.
Figure 9-15. Stop Mode Entry Timing
Figure 9-15
STOP + 2
STOP RECOVERY PERIOD
PREVIOUS DATA
STOP + 2
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SP
SP – 1
SAME
MC68HC908AS60 — Rev. 1.0
SP – 2
SAME
SAME
SP – 3
SAME