mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 384

no-image

mc68hc908as60

Manufacturer Part Number
mc68hc908as60
Description
Mc68hc908as60 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908AS60
Manufacturer:
MOT
Quantity:
5 510
Part Number:
MC68HC908AS60
Manufacturer:
MHS
Quantity:
5 510
Company:
Part Number:
mc68hc908as60ACFU
Quantity:
420
Part Number:
mc68hc908as60ACFV
Manufacturer:
MOTOROLA
Quantity:
1 000
Part Number:
mc68hc908as60AVFU
Manufacturer:
MOTOROLA
Quantity:
547
Part Number:
mc68hc908as60CFN
Manufacturer:
MOT
Quantity:
5 510
Part Number:
mc68hc908as60CFN
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
mc68hc908as60VFN
Manufacturer:
MOT
Quantity:
20 000
Freescale Semiconductor, Inc.
Timer Interface Module A (TIMA-6)
Setting the MS2B bit in TIMA channel 2 status and control register
(TASC2) links channel 2 and channel 3. The output compare value in the
TIMA channel 2 registers initially controls the output on the
PTF0/TACH2 pin. Writing to the TIMA channel 3 registers enables the
TIMA channel 3 registers to synchronously control the output after the
TIMA overflows. At each subsequent overflow, the TIMA channel
registers (2 or 3) that control the output are the ones written to last.
TASC2 controls and monitors the buffered output compare function, and
TIMA channel 3 status and control register (TASC3) is unused. While the
MS2B bit is set, the channel 3 pin, PTF1/TACH3, is available as a
general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered output compare
channel whose output appears on the PTF2 pin. The TIMA channel
registers of the linked pair alternately control the output.
Setting the MS4B bit in TIMA channel 4 status and control register
(TSC4) links channel 4 and channel 5. The output compare value in the
TIMA channel 4 registers initially controls the output on the PTF2 pin.
Writing to the TIMA channel 5 registers enables the TIMA channel 5
registers to synchronously control the output after the TIMA overflows.
At each subsequent overflow, the TIMA channel registers (4 or 5) that
control the output are the ones written to last. TASC4 controls and
monitors the buffered output compare function, and TIMA channel 5
status and control register (TASC5) is unused. While the MS4B bit is set,
the channel 5 pin, PTF3, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. Writing to the active
channel registers is the same as generating unbuffered output
compares.
Technical Data
MC68HC908AS60 — Rev. 1.0
Timer Interface Module A (TIMA-6)
For More Information On This Product,
Go to: www.freescale.com

Related parts for mc68hc908as60