mc68hc908mr8 Freescale Semiconductor, Inc, mc68hc908mr8 Datasheet - Page 93

• Manufacturer Part Number: mc68hc908mr8
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.3 SIM Bus Clock Control and Generation
7.3.1 Bus Timing
7.3.2 Clock Startup from POR or LVI Reset
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
OSC1
PLL
CGMVCLK
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
from either an external oscillator or from the on-chip phase-locked loop
(PLL). See
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 CGMXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The IBUS clocks start upon completion of the
timeout.
SELECT
CIRCUIT
CLOCK
USER MODE
BCS
CGM
MONITOR MODE
Figure 7-3. CGM Clock Signals
System Integration Module (SIM)
Section 8. Clock Generator Module
÷ 2
Section 8. Clock Generator Module
A
B S*
*When S = 1,
CGMOUT = B
CGMXCLK
CGMOUT
SIM Bus Clock Control and Generation
Figure
System Integration Module (SIM)
7-3. This clock can come
÷ 2
SIM COUNTER
(CGM).
SIM
GENERATORS
BUS CLOCK
(CGM).
Technical Data
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