mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 127
mc68hc05jb4p
Manufacturer Part Number
mc68hc05jb4p
Description
Mc68hc705jb4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC05JB4P.pdf
(134 pages)
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A.1
A.2
A.3
MC68HC05JB4
REV 2
This appendix describes the MC68HC705JB4, the emulation part for
MC68HC05JB4. The entire MC68HC05JB4 data sheet applies to the
MC68HC705JB4, with exceptions outlined in this appendix.
INTRODUCTION
The MC68HC705JB4 is an EPROM version of the MC68HC05JB4, and is avail-
able for user system evaluation and debugging. The MC68HC705JB4 is function-
ally identical to the MC68HC05JB4 with the exception of the 3584 bytes user
ROM is replaced by 3584 bytes user EPROM. Also, the mask options available on
the MC68HC05JB4 are implemented using the Mask Option Register (MOR) in
the MC68HC705JB4.
MEMORY
The MC68HC705JB4 memory map is shown in Figure A-1.
MASK OPTION REGISTER (MOR)
The Mask Option Register (MOR) is a byte of EPROM used to select the features
controlled by mask options on the MC68HC05JB4. In order to program this regis-
ter the MORON bit in PCR need to be set to “1” before doing the EPROM pro-
gramming process.
COPEN – COP Enable
IRQTRIG – IRQ, PA0-PA3 Interrupt Options
HIGHCURRA – PA6 and PA7 High Current Enable
MOR
$007F
reset:
1 = COP watchdog function disabled.
0 = COP watchdog function enabled.
1 = Edge-trigger only.
0 = Edge-and-level-triggered.
1 = High current capability disabled on PA6 and PA7.
0 = High current capability enabled on PA6 and PA7.
W
R
BIT 7
0
Freescale Semiconductor, Inc.
For More Information On This Product,
BIT 6
0
Go to: www.freescale.com
MC68HC705JB4
APPENDIX A
February 24, 1999
COPEN
BIT 5
1
IRQTRIG
BIT 4
1
HIGHCURRA
GENERAL RELEASE SPECIFICATION
BIT 3
1
PAINTEN OSCDLY
BIT 2
1
BIT 1
1
LVREN
BIT 0
1
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