mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 93

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

10.6.1.2 Transmit Control Endpoint 0
10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2
10.6.2 Resume Interrupt
10.6.3 End of Packet Interrupt
MC68HC05JB4
REV 2
a SETUP interrupt are shown in Figure 10-30.
For a Control IN transaction directed at Endpoint 0, the USB module will generate
an interrupt by setting the TXD0F flag in the UIR0 register. The conditions
necessary for the interrupt to occur are shown in the flowchart of Figure 10-31.
Transmit Endpoints 1 & 2 share their interrupt flag. For an IN transaction directed
at Endpoint 1 or 2, the USB module will generate an interrupt by setting the
TXD1F flag in the UIR1 register. The conditions necessary for the interrupt to
occur are shown in the flowchart of Figure 10-32.
The USB module will generate a USB interrupt if low speed bus activity is
detected after entering the suspend state. A transition of the USB data lines to the
non-idle state (“K” state) while in the suspend mode will set the RESUMF flag in
the UIR1 register. There is no interrupt enable bit for this interrupt source and an
interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can
only occur while the MC68HC05JB4 is in the suspend mode.
The USB module can generate a USB interrupt upon detection of an end of
packet signal (a single ended 0) for low speed devices. Upon detection of an SE0
sequence, the USB module sets the EOPF bit and will generate an interrupt if the
EOPIE bit in the UIR1 register is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
UNIVERSAL SERIAL BUS MODULE
Go to: www.freescale.com
February 24, 1999
GENERAL RELEASE SPECIFICATION