mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 87

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

10.5.4 USB Control Register 0 (UCR0)
MC68HC05JB4
REV 2
EOPF — End of Packet Detect Flag
RESUMF — Resume Flag
RESUMFR — Resume Flag Reset
TXD1IE — Endpoint 1/Endpoint 2 Transmit Interrupt Enable
EOPIE — End of Packet Detect Interrupt Enable
TXD1FR — Endpoint 1/Endpoint 2 Transmit Flag Reset
EOPFR — End of Packet Flag Reset
UCR0
$003B
This read only bit is set when a valid End-of-Packet sequence is detected on
the D+ and D– lines. Software must clear this flag by writing a logic 1 to the
EOPFR bit.
Reset clears this bit. Writing a logic 0 to EOPF has no effect.
This read only bit is set when USB bus activity is detected while the SUSPND
bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit.
Reset clears this bit. Writing a logic 0 to RESUMF has no effect.
Writing a logic 1 to this write only bit will clear the RESUMF bit if it is set. Writ-
ing a logic 0 to RESUMFR has no effect. Reset clears this bit.
This read/write bit enables the USB to generate an interrupt when the shared
Transmit Endpoint 1/Endpoint 2 interrupt flag (TXD1F) bit becomes set. Reset
clears this bit.
This read/write bit enables the USB to generate an interrupt when the EOPF bit
becomes set. Reset clears this bit.
Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing a
logic 0 to TXD1FR has no effect. Reset clears this bit.
Writing a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing a
logic 0 to the EOPFR has no effect. Reset clears this bit.
reset:
1 = End-of-Packet sequence has been detected
0 = End-of-Packet sequence has not been detected
1 = USB bus activity has been detected
0 = No USB bus activity has been detected
1 = USB interrupts enabled for Transmit Endpoints 1 and 2
0 = USB interrupts disabled for Transmit Endpoints 1 and 2
1 = USB interrupts enabled for Transmit Endpoints 1 and 2
0 = USB interrupts disabled for Transmit Endpoint 1 and 2
W
R
T0SEQ
BIT 7
0
Freescale Semiconductor, Inc.
Figure 10-23. USB Control Register 0 (UCR0)
For More Information On This Product,
STALL0
UNIVERSAL SERIAL BUS MODULE
BIT 6
0
Go to: www.freescale.com
February 24, 1999
TX0E
BIT 5
0
RX0E
BIT 4
0
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
GENERAL RELEASE SPECIFICATION
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0