mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 35

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.5.2 External Interrupt IRQ2
MC68HC05JB4
REV 2
PA0
PA1
PA2
PA3
IRQ
The IRQE enable bit controls whether an active IRQF flag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specified by the contents of $1FFA and $1FFB.
If IRQF is set, the only way to clear this flag is by writing a logic one to the IRQR
acknowledge bit in the ICSR. As long as the output state of the IRQF flag bit is
active the CPU will continuously re-enter the IRQ interrupt sequence until the
active state is removed or the IRQE enable bit is cleared.
The IRQ2/PA4 pin provides an asynchronous interrupt to the CPU. When a nega-
tive-edge is detected by the schmitt trigger input, an IRQ2 interrupt will be gener-
ated if the IRQ2E-bit in the ICSR register is set. This interrupt is serviced by the
interrupt service routine located at the address specified by the contents of $1FFA
and $1FFB. A block diagram of the IRQ2 function is shown in Figure 4-4.
Port A External Interrupt
(Mask Option)
Figure 4-3. External Interrupt (IRQ) Logic
Freescale Semiconductor, Inc.
(Mask Option)
For More Information On This Product,
IRQ Level
IRQ VECTOR FETCH
INTERNAL DATA BUS
Go to: www.freescale.com
February 24, 1999
INTERRUPTS
RST
V
DD
LATCH
IRQ
R
IRQ STATUS/CONTROL REGISTER
GENERAL RELEASE SPECIFICATION
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST