mc68hc05jb4p Freescale Semiconductor, Inc, mc68hc05jb4p Datasheet - Page 54

• Manufacturer Part Number: mc68hc05jb4p
• Description: Mc68hc705jb4 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

GENERAL RELEASE SPECIFICATION
8.1
8.2
OVERVIEW
As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by
four. NTF1 has the same phase and frequency as the processor bus clock, PH2,
but continues to run in WAIT mode. The NTF1 drives an 8-bit ripple counter. The
value of this 8-bit ripple counter can be read by the CPU at any time by accessing
the Timer Counter Register (TCNT) at address $09. A timer overflow function is
implemented on the last stage of this 8-bit counter, giving a possible interrupt rate
of f
The last stage of the 8-bit counter also drives a further 7-bit counter. The final four
stages is used by the RTI circuit, giving possible RTI rates of f
2
RTI and TOF enable bits and flags are located in the Timer Control and Status
Register at location $08.
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 128 or 4064 cycles, the power-on reset circuit is released which
again clears the counter chain and allows the device to come out of reset. At this
point, if RESET is not asserted, the timer will start counting up from zero and nor-
mal device operation will begin. If RESET is asserted at any time during operation
the counter chain will be cleared.
COMPUTER OPERATING PROPERLY (COP) WATCHDOG
The COP Watchdog is enabled by a mask option.
The COP Watchdog Timer function is implemented by using the output of the RTI
circuit and further dividing it by eight. The minimum COP reset rates are listed in
Table 8-1. If the COP circuit times out, an internal reset is generated and the nor-
mal reset vector is fetched.
Preventing a COP time-out is done by writing a “0” to bit-0 of address $1FF0.
When the COP is cleared, only the final divide by eight stage (output of the RTI) is
cleared.
17
OP
, selected by RT1 and RT0 (see Table 8-1). The RTI rate selector bits, and the
÷1024.
RT1
0
0
1
1
Table 8-1. RTI and COP Rates at f
Freescale Semiconductor, Inc.
RT0
0
1
0
1
For More Information On This Product,
Divide Ratio
Go to: www.freescale.com
MULTI-FUNCTION TIMER
2
2
2
2
14
15
16
17
February 24, 1999
Bus Frequency, f
RTI Rate
10.92ms
21.85ms
43.69ms
5.46ms
BUS
=f
OP
OP
=3.0 MHz
COP Reset Period
=3.0MHz
349.52ms
(RTI x 8)
43.68ms
87.36ms
174.8ms
OP
÷2
14
, 2
15
, 2
REV
16
or