dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 19

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dp83848qsqx/nopb

Manufacturer Part Number
dp83848qsqx/nopb
Description
Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
Manufacturer
National Semiconductor Corporation
Datasheet
9.3.3 Serial Management Preamble Suppression
The DP83848Q supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Register
(BMSR, address 01h.) If the station management entity (i.e.
MAC or other management controller) determines that all
PHYs in the system support Preamble Suppression by re-
turning a one in this bit, then the station management entity
need not generate preamble for each management transac-
tion.
The DP83848Q requires a single initialization sequence of 32
bits of preamble following hardware/software reset. This re-
FIGURE 4. Typical MDC/MDIO Write Operation
19
quirement is generally met by the mandatory pull-up resistor
on MDIO in conjunction with a continuous MDC, or the man-
agement access made to determine whether Preamble Sup-
pression is supported.
While the DP83848Q requires an initial preamble sequence
of 32 bits for management initialization, it does not require a
full 32-bit sequence between each subsequent transaction. A
minimum of one idle bit between management transactions is
required as specified in the IEEE 802.3u specification.
30152505
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