dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 27

• Manufacturer Part Number: dp83848qsqx/nopb
• Description: Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
• Manufacturer: National Semiconductor Corporation

10.3.7 Automatic Link Polarity Detection and Correction
The DP83848Q's 10BASE-T transceiver module incorpo-
rates an automatic link polarity detection circuit. When three
consecutive inverted link pulses are received, bad polarity is
reported.
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame (MDF)
or patch panel in the wiring closet.
The bad polarity condition is latched in the 10BTSCR register.
The DP83848Q's 10BASE-T transceiver module corrects for
this error internally and will continue to decode received data
correctly. This eliminates the need to correct the wiring error
immediately.
10.3.8 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83848Q, as the required signal conditioning is integrated
into the device.
Only isolation transformers and impedance matching resis-
tors are required for the 10BASE-T transmit and receive
interface. The internal transmit filtering ensures that all the
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harmonics in the transmit signal are attenuated by at least 30
dB.
10.3.9 Transmitter
The encoder begins operation when the Transmit Enable in-
put (TX_EN) goes high and converts NRZ data to pre-em-
phasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is en-
coded for the transmit-driver pair (PMD Output Pair). TXD
must be valid on the rising edge of Transmit Clock (TX_CLK).
Transmission ends when TX_EN deasserts. The last transi-
tion is always positive; it occurs at the center of the bit cell if
the last bit is a one, or at the end of the bit cell if the last bit is
a zero.
10.3.10 Receiver
The decoder detects the end of a frame when no additional
mid-bit transitions are detected. Within one and a half bit times
after the last bit, carrier sense is de-asserted. Receive clock
stays active for five more bit times after CRS goes low, to
guarantee the receive timings of the controller.
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