dp83848qsqx/nopb National Semiconductor Corporation, dp83848qsqx/nopb Datasheet - Page 46

• Manufacturer Part Number: dp83848qsqx/nopb
• Description: Phyter Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
• Manufacturer: National Semiconductor Corporation

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15:5
1:0
Bit
3:2
Bit
Bit
15
14
13
3
2
13.2.6 LED Direct Control Register (LEDCR)
This register provides the ability to directly control the LED output. It does not provide read access to the LED.
4
1
0
13.2.7 PHY Control Register (PHYCR)
This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause
Negotiation status.
ELAST_BUF[1:0]
DRV_LNKLED
RX_OVF_STS
RX_UNF_STS
RESERVED
RESERVED
RESERVED
Bit Name
Bit Name
LNKLED
FORCE_MDIX
PAUSE_RX
MDIX_EN
Bit Name
TABLE 26. LED Direct Control Register (LEDCR), address 0x18h
TABLE 27. PHY Control Register (PHYCR), address 0x19h
Default
01, RW
Default
0, RW
0, RW
0, RO
0, RO
0, RO
0, RO
0, RO
Strap, RW
Default
0, RW
0, RO
RX FIFO Over Flow Status:
0 = Normal.
1 = Overflow detected.
RX FIFO Under Flow Status:
0 = Normal.
1 = Underflow detected.
Receive Elasticity Buffer:
This field controls the Receive Elasticity Buffer which allows for frequency
variation tolerance between the 50 MHz RMII clock and the recovered data. The
following values indicate the tolerance in bits for a single packet. The minimum
setting allows for standard Ethernet frame sizes at +/-50ppm accuracy for both
RMII and Receive clocks. For greater frequency tolerance the packet lengths may
be scaled (i.e. for +/-100ppm, the packet lenths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2bit tolerance (up to 2400 byte packets)
10 = 6bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
RESERVED: Writes ignored, read as 0.
1 = Drive value of LNKLED bit onto LED_LINK output.
0 = Normal operation.
RESERVED: Writes ignored, read as 0. Value to force on LED_LINK output.
Value to force on LED_LINK output.
RESERVED: Writes ignored, read as 0.
Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit
in the BMCR register to be set. If Auto-Negotiation is not enabled, Auto-
MDIX should be disabled as well.
Force MDIX:
1 = Force MDI pairs to cross.
0 = Normal operation.
Pause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based on
ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest
Common Denominator is a full duplex technology.
46
(Receive on TPTD pair, Transmit on TPRD pair)
Description
Description
Description