adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 23

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

PLL Lock Acquisition
During the lock acquisition period, only Register R0 (Address
0x4000) and Register R1 (Address 0x4002) are accessible
through the control port. Do not attempt to access any other
re ister; any read or write is prohibited until the
enable bit (COREN) and the lock bit a
g
re both asserted.
core clock
Rev. 0 | Page 23 of 80
To program the PLL during initialization or reconfiguration of
the clock setting, the following proce
1.
2.
3.
4.
5.
The PLL control register (Register R1, Address 0x4002) is a
48-bit register where all bits must be written with a single
continuous write to the control p
Power down the PLL.
Reset the PLL control register.
Start the PLL.
Poll the lock bit.
Assert the core clock enable after the PLL lock is acquired.
ort.
dure must be followed:
ADAU1361