adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 58

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

ADAU1361
R18: Converter Control 1 16408 (0x4018)
Bit 7
Table 45. Converter Control 1 Register
Bit
[5:4]
[3:2]
[1:0]
R
Bit 7
Reserved
Table 46. ADC Control Register
Bit
6
5
4
3
2
[1:0]
19: AD Control 16409
C
Bit Name
DAMUTE[1:0]
ADMUTE[1:0]
ADPAIR[1:0]
Bit Name
ADCPOL
HPF
DMPOL
DMSW
INSEL
ADCEN[1:0]
Reserved
Bit 6
Bit 6
ADCPOL
Description
Invert input polarity.
0 = normal (default).
1 = inverted.
ADC high-pass filter select. At 48 kHz, f
0 = off (default).
1 = on.
Digital microphone data polarity swap.
0 = invert polarity.
1 = normal (default).
Digital microphone channel swap. Normal operation sends the left channel on the rising edge and the right
channel on the falling edge of the clock.
0 = normal (default).
1 = swap left and right channels.
Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × f
ADC_SDATA is expected to have left and right channels interleaved.
0 = digital microphone inputs off, ADCs enabled (default).
1 = digital microphone inputs enabled, ADCs off.
ADC enable.
Setting
00
01
10
11
Description
DAC mute.
Setting
00
01
10
11
ADC mute.
Setting
00
01
10
11
On-chip ADC serial data selection in TDM 4 or TDM 8 mode.
Setting
00
01
10
11
(0x4
019)
Bit 5
Bit 5
HPF
DAMUT
E[1:0]
Bit 4
Bit 4
DMPO
Mute/Unmute
Unmute both channels (default)
Right channel mute
Left channel mute
Right and left channel mute
Mute/Unmute
Unmute both channels (default)
Right channel mute
Left channel mute
Right and left channel mute
Pair
First pair (default)
Second pair
Third pair
Fourth pair
L
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ADCs Enabled
Both off (default)
Left on
Right on
Both on
3dB
= 2 Hz.
Bit 3
Bit 3
DMSW
ADMUTE[1:0]
Bit 2
Bi
IN
t 2
SEL
Bit 1
Bit 1
ADPA
ADCEN[1:0]
IR[1:0]
Bit 0
Bit 0
S
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