adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 25

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

PLL
The PLL uses the MCLK as a reference to generate the co
clock. PLL settings are set in Register R1 (PLL control register,
Address 0x4002). Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × f
For example, if MCLK = 12.288 MHz and f
In integer mode, the values set for N and M are ignored.
Tab
Bits
[47:32]
[31:16]
[14:11]
[10:9]
8
1
0
le 15. PLL Control Registe
PLL required output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
MCLK
Bit Name
M[15:0]
N[15:0]
R[3:0]
X[1:0]
Type
Lock
PLLEN
Figure 29. PLL Block Diagram
÷ X
S
).
× (R + N/M)
r (Register R1, Address 0x4002)
Description
Denominator of the fractio
0x00FD: M = 253 (default)
Numerator of the fractional
0x000C: N = 12 (default)
Integer part of PLL: 4 bits, o
0010: R = 2 (de
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R =
PLL input clock divider
00: X = 1 (default)
01: X = 2
10: X = 3
11: X = 4
PLL operation mode
0: Integer (default)
1: Fractional
PLL lock (read-only bit)
0: PLL unlocked (default)
1: PLL locked
PLL enable
0: PLL disabled (default)
1: PLL enabled
CLOCK DIVIDER
S
TO PLL
= 48 kHz, then
8
fault)
re
Rev. 0 | Page 25 of 80
nal PLL: 16-bit binary number
nly values 2 to 8 are valid
PLL: 16-bit binary number
Fractional Mode
Fractional mode is used when the MCLK is a fractional (R +
(N/M)) multiple of the PLL output.
For example, if MCLK = 12 MHz and f
Common
48 kHz sampling rates can be found in Table 16 and Table 17.
The PLL outputs a clock i
which should be taken in
values and MCLK frequencies.
PLL required output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
fractional PLL parameter settings for 44.1 kHz and
to account when calculating PLL
n the range of 41 MHz to 54 MHz,
S
= 48 kHz, then
ADAU1361